The present invention relates to a BS digital broadcast receiver, and more particularly to a BS digital broadcast receiver having a phase error table to be used for carrier reproduction.
A BS digital broadcast system adopts as its modulation scheme Trellis coding 8PSK (simply called also Trellis 8PSK) modulation scheme which is one of coding modulation schemes.
For Trellis decoding by a Viterbi decoder of a conventional BS digital broadcast receiver, as shown in FIG. 8, baseband demodulation signals I and Q demodulated from a reception signal converted into an intermediate frequency signal are supplied to an 8PSK demapper 31 which converts them into tri-bit data (MSB, CSB, LSB) and supplies them to delay circuits 32 to 34 to delay them. The baseband demodulation signals I and Q are also supplied to a QPSK mapping conversion circuit 35. The QPSK mapping conversion circuit 35 converts the signals I and Q into baseband demodulation signals Ixe2x80x2 and Qxe2x80x2 of QPSK and outputs them. The QPSK mapping conversion circuit 35 also outputs I-axis code data and Q-axis code data representative of the position of a reception signal point to be used for detecting whether the position of the reception point belongs to which quadrant, to delay circuits 36 and 37 to delay them.
The baseband demodulation signals Ixe2x80x2 and Qxe2x80x2 output from the QPSK mapping conversion circuit 35 are supplied to a Viterbi decoder 40 to Viterbi-decode them and output decoded data which is also supplied to a convolution encoder 41 to reencode them.
The delay time set to the delay circuits 32 to 34 and delay circuits 36 and 37 is a total sum of a time taken for the Viterbi decoder 40 to decode and a time taken for the convolution encoder 41 to reencode.
The tri-bit data (MSB, CSB, LSB) delayed by the delay circuits 32 to 34, the I-axis code data and Q-axis code data delayed by the delay circuits 36 and 37, and the convolution reencode outputs (TCD1, TCD0) are supplied to an MSB code judging/error detecting circuit 42 which obtains a most significant bit TCD2 and error flags of Trellis decoding. Demapping means to rearrange mapping of the relation between a reception signal and its phase.
As described above, for Trellis decoding in the conventional BS digital broadcast receiver, it is necessary to delay the demapped tri-bit data and the I-axis code data and Q-axis code data by a time equal to the total sum of the time for the Viterbi decoder to decide a path and the time for the convolution reencoding. Five delay circuits are therefore required.
It is an object of the present invention to provide a BS digital broadcast receiver capable of dispensing with an 8PSK demapper and reducing the number of delay circuits used for Trellis encoding.
A BS digital broadcast receiver for receiving a Trellis 8PSK modulation signal, as recited in claim 1 of this invention, comprises:
phase error data generating means for generating phase error data in accordance with a phase difference between 0 degree and a phase of a reception signal point position, in order to reproduce a carrier;
a Viterbi decoder for Viterbi-decoding a QPSK baseband signal based upon a reception signal point position of an absolute-phased baseband demodulation signal;
an encoder for convolution-encoding a Viterbi decode output;
delay means for delaying a predetermined number of upper bits of the phase error data corresponding to the phase difference between 0 degree and the phase of the reception signal point position, by a total sum of a time taken by said Viterbi decoder to Viterbi-decode and a time taken by said convolution encoder to convolution-encode;
a demapping conversion circuit for demapping outputs from said delay means; and
an MSB code judging circuit for outputting a code determined from an output of said demapping conversion circuit and a convolution encode output, as an MSB of a Trellis 8PSK decode output.
According to the BS digital broadcast receiver as recited in claim 1 of this invention, the QPSK baseband signal based upon a reception signal point position of an absolute-phased baseband demodulation signal is Viterbi-decoded by the Viterbi-decoder. An output of the Viterbi-decoder is convolution-reencoded by a convolution encoder. A predetermined number of upper bits of phase error data corresponding to a phase difference between 0 degree and a phase of a phase error detection reception signal point position, is delayed by delay means for carrier reproduction, by a total sum of a time taken by the Viterbi decoder to Viterbi-decode and a time taken by the convolution encoder to convolution-encode. The delayed outputs from the delay means are demapped by the demapped value conversion circuit. A code determined from the demapped output and convolution encode output is output as an MSB of a Trellis 8PSK decode output from the MSB code judging/error detecting circuit.
Therefore, according to the BS digital broadcast receiver as recited in claim 1 of this invention, an 8PSK demapper conventionally required can be dispensed with and the number of delay circuits to be used for Trellis encoding is only the number of delay circuits predetermined for particular phase error data to thereby reduce the number of delay circuits.
In the BS digital broadcast receiver as recited in claim 1 of this invention, the predetermined number of upper bits may be four bits, the MSB code judging circuit may compare a reception signal point position on a Trellis 8PSK mapping having lower two bits same as a Viterbi decode output with an MSB judging demapped value on an MSB judging circle obtained by rotating the Trellis 8PSK mapping by 22.5 degrees, judge a reception signal point position having a shorter distance as a judged position, and if an MSB of the judged position is not same as an MSB of the MSB judging demapped value, invert the MSB of the MSB judging demapped value and outputs the inverted MSB as a judged MSB.